MIPS in PS2DIS

[JohnnyMcKinney]

Here are the MIPS that you will see in PS2DIS. This should better help you understand their purpose.

ADD - Add
Description: Adds two registers and stores the result in a register
Operation: $d = $s + $t; advance_pc (4);
Syntax: add $d, $s, $t
Encoding: 0000 00ss ssst tttt dddd d000 0010 0000


ADDI - Add immediate
Description: Adds a register and a signed immediate value and stores the result in a register
Operation: $t = $s + imm; advance_pc (4);
Syntax: addi $t, $s, imm
Encoding: 0010 00ss ssst tttt iiii iiii iiii iiii


ADDIU - Add immediate unsigned
Description: Adds a register and an unsigned immediate value and stores the result in a register
Operation: $t = $s + imm; advance_pc (4);
Syntax: addiu $t, $s, imm
Encoding: 0010 01ss ssst tttt iiii iiii iiii iiii


ADDU - Add unsigned
Description: Adds two registers and stores the result in a register
Operation: $d = $s + $t; advance_pc (4);
Syntax: addu $d, $s, $t
Encoding: 0000 00ss ssst tttt dddd d000 0010 0001


AND - Bitwise and
Description: Bitwise ands two registers and stores the result in a register
Operation: $d = $s & $t; advance_pc (4);
Syntax: and $d, $s, $t
Encoding: 0000 00ss ssst tttt dddd d000 0010 0100


ANDI - Bitwise and immediate
Description: Bitwise ands a register and an immediate value and stores the result in a register
Operation: $t = $s & imm; advance_pc (4);
Syntax: andi $t, $s, imm
Encoding: 0011 00ss ssst tttt iiii iiii iiii iiii


BEQ - Branch on equal
Description: Branches if the two registers are equal
Operation: if $s == $t advance_pc (offset << 2)); else advance_pc (4);
Syntax: beq $s, $t, offset
Encoding: 0001 00ss ssst tttt iiii iiii iiii iiii


BGEZ - Branch on greater than or equal to zero
Description: Branches if the register is greater than or equal to zero
Operation: if $s >= 0 advance_pc (offset << 2)); else advance_pc (4);
Syntax: bgez $s, offset
Encoding: 0000 01ss sss0 0001 iiii iiii iiii iiii


BGEZAL - Branch on greater than or equal to zero and link
Description: Branches if the register is greater than or equal to zero and saves the return address in $31
Operation: if $s >= 0 $31 = PC + 8 (or nPC + 4); advance_pc (offset << 2)); else advance_pc (4);
Syntax: bgezal $s, offset
Encoding: 0000 01ss sss1 0001 iiii iiii iiii iiii


BGTZ - Branch on greater than zero
Description: Branches if the register is greater than zero
Operation: if $s > 0 advance_pc (offset << 2)); else advance_pc (4);
Syntax: bgtz $s, offset
Encoding: 0001 11ss sss0 0000 iiii iiii iiii iiii


BLEZ - Branch on less than or equal to zero
Description: Branches if the register is less than or equal to zero
Operation: if $s <= 0 advance_pc (offset << 2)); else advance_pc (4);
Syntax: blez $s, offset
Encoding: 0001 10ss sss0 0000 iiii iiii iiii iiii


BLTZ - Branch on less than zero
Description: Branches if the register is less than zero
Operation: if $s < 0 advance_pc (offset << 2)); else advance_pc (4);
Syntax: bltz $s, offset
Encoding: 0000 01ss sss0 0000 iiii iiii iiii iiii


BLTZAL - Branch on less than zero and link
Description: Branches if the register is less than zero and saves the return address in $31
Operation: if $s < 0 $31 = PC + 8 (or nPC + 4); advance_pc (offset << 2)); else advance_pc (4);
Syntax: bltzal $s, offset
Encoding: 0000 01ss sss1 0000 iiii iiii iiii iiii


BNE - Branch on not equal
Description: Branches if the two registers are not equal
Operation: if $s != $t advance_pc (offset << 2)); else advance_pc (4);
Syntax: bne $s, $t, offset
Encoding: 0001 01ss ssst tttt iiii iiii iiii iiii


DIV - Divide
Description: Divides $s by $t and stores the quotient in $LO and the remainder in $HI
Operation: $LO = $s / $t; $HI = $s % $t; advance_pc (4);
Syntax: div $s, $t
Encoding: 0000 00ss ssst tttt 0000 0000 0001 1010


DIVU - Divide unsigned
Description: Divides $s by $t and stores the quotient in $LO and the remainder in $HI
Operation: $LO = $s / $t; $HI = $s % $t; advance_pc (4);
Syntax: divu $s, $t
Encoding: 0000 00ss ssst tttt 0000 0000 0001 1011


J - Jump
Description: Jumps to the calculated address
Operation: PC = nPC; nPC = (PC & 0xf0000000) | (target << 2);
Syntax: j target
Encoding: 0000 10ii iiii iiii iiii iiii iiii iiii


JAL - Jump and link
Description: Jumps to the calculated address and stores the return address in $31
Operation: $31 = PC + 8 (or nPC + 4); PC = nPC; nPC = (PC & 0xf0000000) | (target << 2);
Syntax: jal target
Encoding: 0000 11ii iiii iiii iiii iiii iiii iiii


JR - Jump register
Description: Jump to the address contained in register $s
Operation: PC = nPC; nPC = $s;
Syntax: jr $s
Encoding: 0000 00ss sss0 0000 0000 0000 0000 1000


LB - Load byte
Description: A byte is loaded into a register from the specified address.
Operation: $t = MEM[$s + offset]; advance_pc (4);
Syntax: lb $t, offset($s)
Encoding: 1000 00ss ssst tttt iiii iiii iiii iiii


LUI - Load upper immediate
Description: The immediate value is shifted left 16 bits and stored in the register. The lower 16 bits are zeroes.
Operation: $t = (imm << 16); advance_pc (4);
Syntax: lui $t, imm
Encoding: 0011 11-- ---t tttt iiii iiii iiii iiii


LW - Load word
Description: A word is loaded into a register from the specified address.
Operation: $t = MEM[$s + offset]; advance_pc (4);
Syntax: lw $t, offset($s)
Encoding: 1000 11ss ssst tttt iiii iiii iiii iiii


MFHI - Move from HI
Description: The contents of register HI are moved to the specified register.
Operation: $d = $HI; advance_pc (4);
Syntax: mfhi $d
Encoding: 0000 0000 0000 0000 dddd d000 0001 0000


MFLO - Move from LO
Description: The contents of register LO are moved to the specified register.
Operation: $d = $LO; advance_pc (4);
Syntax: mflo $d
Encoding: 0000 0000 0000 0000 dddd d000 0001 0010


MULT - Multiply
Description: Multiplies $s by $t and stores the result in $LO.
Operation: $LO = $s * $t; advance_pc (4);
Syntax: mult $s, $t
Encoding: 0000 00ss ssst tttt 0000 0000 0001 1000


MULTU - Multiply unsigned
Description: Multiplies $s by $t and stores the result in $LO.
Operation: $LO = $s * $t; advance_pc (4);
Syntax: multu $s, $t
Encoding: 0000 00ss ssst tttt 0000 0000 0001 1001


NOP - no operation
Description: Performs no operation.
Operation: advance_pc (4);
Syntax: nop
Encoding: 0000 0000 0000 0000 0000 0000 0000 0000


Note: The encoding for a NOOP represents the instruction SLL $0, $0, 0 which has no side effects. In fact, nearly every instruction that has $0 as its destination register will have no side effect and can thus be considered a NOOP instruction.


OR - Bitwise or
Description: Bitwise logical ors two registers and stores the result in a register
Operation: $d = $s | $t; advance_pc (4);
Syntax: or $d, $s, $t
Encoding: 0000 00ss ssst tttt dddd d000 0010 0101


ORI - Bitwise or immediate
Description: Bitwise ors a register and an immediate value and stores the result in a register
Operation: $t = $s | imm; advance_pc (4);
Syntax: ori $t, $s, imm
Encoding: 0011 01ss ssst tttt iiii iiii iiii iiii


SB - Store byte
Description: The least significant byte of $t is stored at the specified address.
Operation: MEM[$s + offset] = (0xff & $t); advance_pc (4);
Syntax: sb $t, offset($s)
Encoding: 1010 00ss ssst tttt iiii iiii iiii iiii


SLL - Shift left logical
Description: Shifts a register value left by the shift amount listed in the instruction and places the result in a third register. Zeroes are shifted in.
Operation: $d = $t << h; advance_pc (4);
Syntax: sll $d, $t, h
Encoding: 0000 00ss ssst tttt dddd dhhh hh00 0000


SLLV - Shift left logical variable
Description: Shifts a register value left by the value in a second register and places the result in a third register. Zeroes are shifted in.
Operation: $d = $t << $s; advance_pc (4);
Syntax: sllv $d, $t, $s
Encoding: 0000 00ss ssst tttt dddd d--- --00 0100


SLT - Set on less than (signed)
Description: If $s is less than $t, $d is set to one. It gets zero otherwise.
Operation: if $s < $t $d = 1; advance_pc (4); else $d = 0; advance_pc (4);
Syntax: slt $d, $s, $t
Encoding: 0000 00ss ssst tttt dddd d000 0010 1010


SLTI - Set on less than immediate (signed)
Description: If $s is less than immediate, $t is set to one. It gets zero otherwise.
Operation: if $s < imm $t = 1; advance_pc (4); else $t = 0; advance_pc (4);
Syntax: slti $t, $s, imm
Encoding: 0010 10ss ssst tttt iiii iiii iiii iiii


SLTIU - Set on less than immediate unsigned
Description: If $s is less than the unsigned immediate, $t is set to one. It gets zero otherwise.
Operation: if $s < imm $t = 1; advance_pc (4); else $t = 0; advance_pc (4);
Syntax: sltiu $t, $s, imm
Encoding: 0010 11ss ssst tttt iiii iiii iiii iiii


SLTU - Set on less than unsigned
Description: If $s is less than $t, $d is set to one. It gets zero otherwise.
Operation: if $s < $t $d = 1; advance_pc (4); else $d = 0; advance_pc (4);
Syntax: sltu $d, $s, $t
Encoding: 0000 00ss ssst tttt dddd d000 0010 1011


SRA - Shift right arithmetic
Description: Shifts a register value right by the shift amount (shamt) and places the value in the destination register. The sign bit is shifted in.
Operation: $d = $t >> h; advance_pc (4);
Syntax: sra $d, $t, h
Encoding: 0000 00-- ---t tttt dddd dhhh hh00 0011


SRL - Shift right logical
Description: Shifts a register value right by the shift amount (shamt) and places the value in the destination register. Zeroes are shifted in.
Operation: $d = $t >> h; advance_pc (4);
Syntax: srl $d, $t, h
Encoding: 0000 00-- ---t tttt dddd dhhh hh00 0010


SRLV - Shift right logical variable
Description: Shifts a register value right by the amount specified in $s and places the value in the destination register. Zeroes are shifted in.
Operation: $d = $t >> $s; advance_pc (4);
Syntax: srlv $d, $t, $s
Encoding: 0000 00ss ssst tttt dddd d000 0000 0110


SUB - Subtract
Description: Subtracts two registers and stores the result in a register
Operation: $d = $s - $t; advance_pc (4);
Syntax: sub $d, $s, $t
Encoding: 0000 00ss ssst tttt dddd d000 0010 0010


SUBU - Subtract unsigned
Description: Subtracts two registers and stores the result in a register
Operation: $d = $s - $t; advance_pc (4);
Syntax: subu $d, $s, $t
Encoding: 0000 00ss ssst tttt dddd d000 0010 0011


SW - Store word
Description: The contents of $t is stored at the specified address.
Operation: MEM[$s + offset] = $t; advance_pc (4);
Syntax: sw $t, offset($s)
Encoding: 1010 11ss ssst tttt iiii iiii iiii iiii


SYSCALL - System call
Description: Generates a software interrupt.
Operation: advance_pc (4);
Syntax: syscall
Encoding: 0000 00-- ---- ---- ---- ---- --00 1100


XOR - Bitwise exclusive or
Description: Exclusive ors two registers and stores the result in a register
Operation: $d = $s ^ $t; advance_pc (4);
Syntax: xor $d, $s, $t
Encoding: 0000 00ss ssst tttt dddd d--- --10 0110


XORI - Bitwise exclusive or immediate
Description: Bitwise exclusive ors a register and an immediate value and stores the result in a register
Operation: $t = $s ^ imm; advance_pc (4);
Syntax: xori $t, $s, imm
Encoding: 0011 10ss ssst tttt iiii iiii iiii iiii

[Zeus]

Niceee. I like it :P But you normally don't use a lot of these.
I normally only see these ones...

LUI
LW
SW
JR RA
JAL
J
ADDU

& of course
NOP

[AlienatedTailz]

Can you maybe post a few examples of what codes belong to which MIPS? I know some boots belong to JALs, but what other ones do the others belong to?

[S1L3NT_K1LL3R]

Well some InfAmmo codes are held in a SW command. Sometimes a subtracting command usually the SW will come after the subtracting command. InfHealth is usually held in a ADDIU that is part of a function sometimes you would use that line or search around that area and check other functions. And lobby boot is just using a hook then a routine that loads the address and adds the boot value to the routine then just stores it in the routine. Color mods are just where you load the color with a float point then the LUI that tells how much color then just add the floats and store them. Thats just about as simple as it gets.

[rufino]

can some1 plz tell me how to put a socom dupm on my comp plz i wanna mke a textmod plz plz

[GuItArMaStA]

uhh porting is so hard

[Dubstepper]

what are mip's sub rutin's good for?

[DeKryption]

what are mip's sub rutin's good for?

MIPs is a language that tells you what the function of that value is doing.

For example:
J $09000000

That is telling PS2DIS to make a value that jumps to the address 0x09000000

[Dubstepper]

ahhhh... i see

[Linblow]

Here is the full list :

ABS.S Floating Point Absolute Value
ADD Add Word
ADD.S Floating Point ADD
ADDI Add Immediate Unsigned Word
ADDIU Add Immediate Unsigned Word
ADDU Add unsigned Word
AND And
ANDI Add immediate
BC0F Branch on Coprocessor 0 False
BC0FL Branch on Coprocessor 0 False Likely
BC0T Branch on Coprocessor 0 True
BC0TL Branch on Coprocessor 0 True Likely
BC1F Branch on FP False
BC1FL Branch on FP False Likely
BC1T Branch on FP True
BC1TL Branch on FP True Likely
BEQ Branch on Equal
BEQL Branch on equal likely
BGEZ Branch on Greater Than or Equal to Zero : Est supérieur ou égal à zero
BGEZAL Branch on Greater Than or Equal to Zero and Link
BGEZALL Branch on Greater Than or Equal to Zero and Link likely
BGEZL Branch on Greater Than or Equal to Zero likely
BGTZ Branch on Greater Than Zero
BGTZL Branch on Greater Than Zero likely
BLEZ Branch on Less Than or equal to Zero
BLEZL Branch on Less Than or equal to Zero likely
BLTZ Branch on Less than Zero
BLTZAL Branch on Less than Zero and Link
BLTZALL Branch on Less than Zero and Link likely
BLTZL Branch on Less than Zero likely
BNE Branch on Not Equal
BNEL Branch on Not Equal likely
BREAK Breakpoint
C.EQ.S Floating Point Compare
C.F.S Floating Point Compare
C.LE.S Floating Point Compare
C.LT.S Floating Point Compare
CFC1 Move Control Word from Floating Point
CTC1 Move Control Word to Floating Point
CVT.S.W Fixed point Convert to Single Floating Point
CVT.W.S Floating Point Convert to Word Fixed point
DADD Doubleword Add
DADDI Doubleword Add Immediate
DADDIU Doubleword Add Immediate Unsigned
DADDU Doubleword Add unsigned
DI Disable Interrupt
DIV Divide Word
DIV1 Divide Word Pipeline 1
DIV.S Floating Point Divide
DIVU Divide Unsigned Word
DIVU1 Divide Unsigned World Pipeline 1
DSLL Doubleword Shift Left logicial
DSLL32 Doubleword Shift Left logicial Plus 32
DSLLV Doubleword Shift Left logicial Variable
DSRA Doubleword Shift Right Arithmetic
DSRA32 Doubleword Shift Right Arithmetic plus 32
DSRAV Doubleword Shift Right Arithmetic variable
DSRL Doubleword Shift Right Logical
DSRL32 Doubleword Shift Right Logical plus 32
DSRLV Doubleword Shift Right Logical Variable
DSUB Doubleword Subtract
DSUBU Doubleword Subtract unsigned
EI Enable Interrupt
ERET Exception Return
J Jump
JAL Jump and Link
JALR Jump and Link Register
JR Jump Register
LB Load Byte
LBU Load Byte Unsigned
LD Load Doubleword
LDL Load Doubleword Left
LDR Load Doubleword Right
LH Load Halfword
LHU Load Halfword Unsigned
LUI Load Upper Immediate
LW Load Word
LWL Load Word Left
LWR Load Word Right
LWU Load Word Unsigned
LWC1 Loading Word to Floating Point
LQ Load Quadword
MADD Multiply Add word
MADD1 Multiply Add Unsigned word
MADD.S Floating Point Multiply ADD
MADDA.S Floating Point Multiply ADD
MADDU Multiply Add Unsigned word
MAX.S Floating Point Maximum
MADDU1 Multiply Add Unsigned word Pipeline 1
MFBPC Move from Breakpoint Control Register
MFC0 Move from System Control Coprocessor
MFDAB Move from Data Address Breakpoint Register
MFDABM Move from Data Address Breakpoint Mask Register
MFDVB Move from Data value Breakpoint Register
MFDVBM Move from Data Value Breakpoint Mask Register
MFIAB Move from Intstruction Address Breakpoint Register
MFIABM Move from Instruction Address Breakpoint Mask Register
MFC1 Move Word from Floating Point
MFPC Move from Performance Counter
MFPS Move from Performance Event Specifier
MIN.S Floating Point Minimum
MTBPC Move to Breakpoint Control Register
MTC0 Move to System Control Coprocessor
MTDAB Move to Data Address Breakpoint Register
MTDABM Move from Data Address Breakpoint Mask Register
MTDVB Move to Data Value Breakpoint Register
MTDVBM Move to Data Value Breakpoint Mask Register
MTIAB Move to Instruction Address Breakpoint Register
MTPC Move to Performance Counter
MTPS Move to Performace Even Specifier
MFHI Move from HI Register
MFHI1 Move From HI1 Register
MFLO Move from LO Register
MFLO1 Move From LO1 Register
MFSA Move from Shift Amount Register
MOV.S
MOVN Move Conditional on Not Zero
MOVZ Move Conditional on Zero
MSUB.S Floating Point Multiply and Subtract
MSUBA.S Floating Point Multiply and Subtract from Accumulator
MTC1 Move Word to Floating Point
MTHI Move to HI Register
MTHI1 Move to HI1 Register
MTLO Move to LO Register
MTLO1 Move To LO1 Register
MTSA Move to Shift Amount Register
MTSAB Move Byte Count to Shift Amount Registter
MTSAH Move Halfword Count to Shift Amount Register
MUL.S Floating Point Multiply
MULA.S Floating Multiply to Accumulator
MULT Multiple Word
MULT1 Multiply Word Pipeline 1
MULTU Multiple Word Unsigned
MULTU1 Multiple Unsigned World Pipeline 1
NEG.S Floating Point Negate
NOR Not Or
OR Or
ORI Or Immediate
PREF Prefetch
PABSH Parellel Absolute Halfword
PABSW Parellel Absolute Word
PADDB Parellel Add Byte
PADDH Parallel Add Halfword
PADDSB Parallel Add with Signed saturation Byte
PADDSH Parallel Add with Signed saturation Halfword
PADDSW Parallel Add with Signed saturation Word
PADDUB Parallel Add with Unsigned saturation Byte
PADDUH Parallel Add with Unsigned saturation Halfword
PADDUW Parallel Add with Unsigned saturation Word
PADDW Parallel Add Word
PADSBH Parallel Add/Subtract Halfword
PAND Parallel And
PCEQB Parallel Compare for Equal Byte
PCEQH Parallel Compare for Equal Halfword
PCEQW Parallel Compare for Equal Word
PCGTB Parallel Compare for Greater Than Byte
PCGTH Parallel Compare for Greater Then Halfowrd
PCGTW Parallel Compare for Greater Than Word
PCPYH Parallel Copy Halfword
PCPYLD Parallel Copy Lower Doubleword
PCPYUD Parallel Copy Upper Doubleword
PDVIBW Parallel Divide Broadcast Word
PDIVUW Parallel Divide Ungisnged Word
PDIVW Parallel Divide Word
PEXCH Parallel Exchange Center Halfword
PEXCW Parallel Exchange Center Word
PEXEH Parallel Exchange Even Halfword
PEXEW Parallel Exchange Even Word
PEXT5 Parallel Extend from 5 bits
PEXTLB Parallel Extend Lower from Byte
PEXTLH Parallel Extend Lower from Halfword
PEXTLW Parallel Extend Lower from Word
PEXTUB Parallel Extend Upper from Byte
PEXTUH Parallel Extend Upper from Halfword
PEXTUW Parallel Extend Upper from Word
PHMADH Parallel Horizontal Multiply Add Halfword
PHMSBH Parallel Horizontal Multiply Subract Halfword
PINTEH Parallel Interleave Even Halfword
PINTH Parallel Interleave Halfword
PLZCW Parallel Leading Zero or one Count Word
PMADDH Parallel Multiply Add Halfword
PMADDUW Parallel Multiply Add Unsigned Word
PMADDW Parallel Multiply Add Word
PMAXH Parallel Maximize Halfword
PMAXW Parallel Maximize Word
PMFHI Parallel Move From HI Register
PMFHL.LH Parallel Move From HI/LO Register
PMFHL.LW Parallel Move From HI/LO Register
PMFHL.SH Parallel Move From HI/LO Register
PMFHL.SLW Parallel Move From HI/LO Register
PMFHL.UW Parallel Move From HI/LO Register
PMFLO Parallel Move From LO Register
PMINH Parallel Minimize Halfword
PMINW Parallel Minimize Word
PMSUBH Parallel Multiply Subract Halfword
PMSUBW Parallel Multiply Subract Word
PMTHI Parallel Move To HI Register
PMTH.LW Parallel Move To HI/LO Register
PMTLO Parallel Move To LO Register
PMULTH Parallel Multiply Halfword
PMULTUW Parallel Multiply Unsigned Word
PMULTw Parallel Multiply Word
PNOR Parallel Not Or
PPAC5 Parallel Pack to 5 bits
PPACB Parallel Pack to Byte
PPACH Parallel Pack to Halfword
PPACW Parallel Pack to Word
PREVH Parallel Reverse Halfword
PROT3W Parallel Rotate 3 Words Left
PSLLH Parallel Shift Left Logical Halfword
PSLLVW Parallel Shift Left Logical Variable Word
PSLLW Parallel Shift Left Logical Word
PSRAH Parallel Shift Right Arithmetic Halfword
PSRAVW Parallel Shift Right Arithmetic Variable Word
PSRAW Parallel Shift Right Arithmetic Word
PSRLH Parallel Shift Right Locial Halfword
PSRLVW Parallel Shift Right Logical Variable Word
PSRLW Parallel Shift Right Logical Word
PSUBB Parallel Subract Byte
PSUBH Parallel Subtract Halfword
PSUBSB Parallel Subtract with Signed saturation Byte
PSUBSH Parallel Subtract with Signed Saturation Halfword
PSUBSW Parallel Subtract with Signed Saturation Word
PSUBUB Parallel Subtract with Unsigned Saturation Byte
PSUBUH Parallel Subtract with Unsigned Saturation Halfword
PSUBUW Parallel Subtract with Unsigned Saturation Word
PSUBW Parallel Subtract Word
PXOR Parallel Exclusive OR
QFSRV Quadword Fnnel Shift Right Variable
RSQRT.S Floating Point Square Root
SB Store Byte
SD Store Doubleword
SDL Store Doubleword Left
SDR Store Doubleword Right
SH Store halfword
SLL Store Word Left Logical
SLLV Store Word Left Logical Variable
SLT Set on Less Than
SLTI Set on Less Than Immediate
SLTIU Set on Less Than Immediate Unsigned
SLTU Set on Less Than Unsigned
SQ Store Quadword
SQRT.S Floating Point Square Root
SRA Shift Word Right Arithmetic
SRAV Shift Word Right Arithmetic Variable
SRL Shift Word Right Logical
SRLV Shift Word Right Logical Variable
SUB Subtract Word
SUB.S Floating Point SUbtract
SUBA.S Floating Point Subtract to Accumulator
SUBU Subtract Unsigned Word
SW Store Word
SWC1 Store Word from Floating Point
SWL Store Word Left
SWR Store Word Right
SYNC Synchronize Shared Memory
SYSCALL System Call
TEQ Trap if Equal
TEQI Trap if Equal Immediate
TGE Trap if Greater or Equal
TGEI Trap if Greater or Equal Immediate
TGEIU Trap if Greater or Equal Immediate Unsigned
TGEU Trap if Greater or Equal Unsigned
TLT Trap if Less Than
TLTI Trap if Less Than Immediate
TLTIU Trap if Less Than Immediate Unsigned
TLTU Trap if Less Than unsigned
TNE Trap if Not Equal
TNEI Trap if Not Equal Immediate
XOR Exclusive OR
XORI Exclusive OR Immediate

Thanks Blueman.